System-on-a-Chip (SoC) devices are widely used for many applications. With integrating cores from different sources to a single chip, the testing of a core-based SoC design becomes more difficult than before. Therefore, IEEE 1500 test standard, i.e. the test standard for core-based design, has been approved by the IEEE (Institute of Electrical and Electrical and Electronic Engineers) to reduce the test complexity of a SoC device, and reuse the test architecture.
FIG. 1 is a schematic view of a test wrapper for the IEEE 1500 standard. The fault coverage of a SoC device can be improved by using this test architecture.
A test wrapper conforming to IEEE 1500 standard is wrapped around a core. The test wrapper includes an n-bit wrapper instruction register (WIR) (not shown) for storing a test instruction, a 1-bit wrapper bypass register (WBY) (not shown), a wrapper boundary register (WBR) for storing test data, a serial interface layer and a set of standard wrapper serial control (WSC), wherein WIR and WBY are included in the serial interface layer. The test circuit can also access data registers inside the core for testing requirement. This type of data register is called a core data register (CDR).
The architecture of the IEEE 1149.1 standard, as shown in FIG. 2, may also be used for testing a core-based design. The IEEE 1149.1 standard is defined for testing and debugging a chip that is mounted on a printed-circuit board (PCB) thereon. The test wrapper complying with the IEEE 1149.1 standard is composed of a set of Test Access Port (TAP) test signals, a boundary scan register (BSR) connecting input/output (I/O) ports to an internal core, an instruction register (IR), a bypass register, and a TAP controller. The TAP test signals are composed of a Test-Data Input (TDI), a Test-Data-Output (TDO), a Test-Mode-Select (TMS), and a Test-Clock (TCK). An optional Test-Reset (TRST) signal is sometimes included to reset test state. The TAP controller is composed of a finite state machine (FSM) and a state register (SR). The TAP controller receives the TMS (, the TRST,) and the TCK signals to control the content of the SR. The state transition graph of the FSM is as shown in FIG. 3. The BSR receives test data from the TDI and outputs test result to the TDO when the SR is in the Shift-DR state. Similarly, the IR receives test instruction from the TDI and outputs test instruction of other core to the TDO when the SR is in the Shift-IR state.
A data register and corresponding test instructions can be self-defined based on the IEEE 1149.1 standard in addition to mandatory and optional instructions and registers predefined in the specification. Test processes and test data paths of an integrated circuit (IC) can be controlled by using the TAP controller. The IEEE 1149.1 standard can be applied to either testing on a PCB or testing and debugging on a core within a SoC.
However, when more cores are integrated into a SoC, control signals complying with the IEEE 1500 standard inside cores of respective wrappers and the total length of the test registers of the cores are linearly and multiply increased, costing much time for inputting wrapper instruction registers complying with the IEEE 1500 standard while test instructions are updated. Thus, a test device and method for the SoC test architecture is desirable, managing controllers of cores and saving test time.